Semiconductor devices are widely used in a host of applications, ranging from computers, micro-controllers, cell phones and communication devices, wired and wireless data networking, consumer electronics, and many other applications. Semiconductor devices are typically fabricated in wafer form. After fabrication, the wafer is “diced” to signulate the individual die along the scribe lines on the wafer. The individual die are then packaged and tested before being sent to customers or end users.
Semiconductor devices can be encapsulated in a number of different types of packages, such as ball grid arrays, quad flat packs, etc. Many of these packaging types require the die to be encapsulated in a molding compound such as epoxy B. With certain types of die, the use of molding material is problematic because it creates stress on the die. This stress, sometimes referred to as “stress buffering”, is caused by physical changes to the compound during the molding and curing process. This phenomena is particularly troublesome with high precision semiconductor devices that are required to sense very low voltages. These devices typically have thin film resistors (TFRs) fabricated thereon and that are used in the sensing of the very low voltages on the die surface. Changes in the resistivity of the thin film resistor caused by the molding process may cause the regulated voltage outputs on the device to vary and not meet device specifications. More specifically, the stress may impact the electrical performance of the device, causing parametric drift and hampering its high precision performance.
A so called “Glob” top packaging technique is one known way of potentially reducing or eliminating the stress buffering situation. With glob top packaging, a ball or glob of stress-free material, such as QI-4939 (silicon gel), is dispensed onto the surface of the die. This material acts as a physical buffer between the thin film resistor and the molding compound. The glob process, however, has a number of drawbacks. Foremost, it is expensive. The glob has to be placed on each individual die, as opposed to applying the material on the wafer level. Thus the process is both time consuming and requires specific or dedicated equipment. It is also difficult to control the height of the glob since it is dispensed onto the die surface. Finally, the glob top packaging technique does not work with all types of package configurations. In some circumstances, the glob interferes with the wire bonding process.
An apparatus and method for packaging semiconductor devices using patterned laminate films to reduce stress buffering is therefore needed.